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DS28CZ04: 4Kb I2C/SMBus EEPROM with Nonvolatile PIO
As a 512 byte memory device, the DS28CZ04 needs 9 address bits to access a memory location. The P0 bit
transmitted in place of the A0 address bit specifies whether the “lower half” (0b) or the “upper half” (1b) of the
memory is addressed. This causes the DS28CZ04 to occupy two logical slave addresses, one for each half of the
memory. Throughout this document, the lower half of the memory is referenced as Device Address A0h and the
upper half as Device Address A2h . The addresses A0h and A2h are correct if the A1 and A2 pins are tied to logic
0. For different conditions at these pins the slave address changes accordingly.
The last bit of the slave-address/direction byte (R/ W ) defines the data direction. When set to a 0, subsequent data
will flow from master to slave (write access mode); when set to a 1, data will flow from slave to master (read access
mode). Although the P0 bit is also transmitted when accessing the DS28CZ04 in read mode, its value is ignored
(don’t care); instead, the value transmitted in the most recent write access applies .
I2C/SMBus Protocol
Data transfers may be initiated only when the bus is not busy. The master generates the serial clock (SCL),
controls the bus access, generates the START and STOP conditions, and determines the number of bytes
transferred on the data line (SDA) between START and STOP. Data is transferred in bytes with the most significant
bit being transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and
slave. During any data transfer, SDA must remain stable whenever the clock line is HIGH. Changes in SDA line
while SCL is high will be interpreted as a START or a STOP. The protocol is illustrated in Figure 5. For detailed
timing references see Figure 6.
Figure 5. I2C/SMBus Protocol Overview
MS-bit
R/ W
ACK
bit
ACK
bit
SDA
Slave Address
Acknowledgment
from Receiver
Repeated if more bytes
are transferred
SCL
1
2
6
7
8
9
1
2
8
9
Idle
START
Condition
ACK
ACK
STOP Condition
Repeated START
Condition
Bus Idle or Not Busy
Both, SDA and SCL, are inactive, i. e., in their logic HIGH states.
START Condition
To initiate communication with a slave, the master has to generate a START condition. A START condition is
defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH.
STOP Condition
To end communication with a slave, the master has to generate a STOP condition. A STOP condition is defined as
a change in state of SDA from LOW to HIGH while SCL remains HIGH.
Repeated START Condition
Repeated starts are commonly used for read accesses after having specified a memory address to read from in a
preceding write access. The master can use a repeated START condition at the end of a data transfer to
immediately initiate a new data transfer following the current one. A repeated START condition is generated the
same way as a normal START condition, but without leaving the bus idle after a STOP condition.
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